{{formatInt(addressValue, (options.extended ? 3 : 2))}}
{{formatInt(dataValue, (options.extended ? 4 : 3))}}
{{controlSignal}}
Settings
Assembly Code
{{narrative}}
CPU
Control Unit
| Opcode | Rd | Rn | Op2 |
| {{formatInt(opcode, 2)}} | {{reg_rd}} | {{reg_rs}} | {{formatInt(reg_tt, 2)}} |
| {{opcodeName}} | R{{reg_rd}} | R{{reg_rs}} | {{irTtDisplay}} |
Registers
| PC
|
{{formatInt(pc, (options.extended ? 3 : 2))}}
|
| IR
|
{{formatInt(ir, 6)}}
|
|
Control Bus
|
|
| R0
|
{{formatInt(registers[0], 2)}}
|
| R1
|
{{formatInt(registers[1], 2)}}
|
| R2
|
{{formatInt(registers[2], 2)}}
|
| R3
|
{{formatInt(registers[3], 2)}}
|
| R4
|
{{formatInt(registers[4], 2)}}
|
| R5
|
{{formatInt(registers[5], 2)}}
|
| R6
|
{{formatInt(registers[6], 2)}}
|
| R7
|
{{formatInt(registers[7], 2)}}
|
| R8
|
{{formatInt(registers[8], 2)}}
|
| R9
|
{{formatInt(registers[9], 2)}}
|
| R10
|
{{formatInt(registers[10], 2)}}
|
| R11
|
{{formatInt(registers[11], 2)}}
|
ALU
| N | Z | C | V |
| {{flagN ? 1 : 0}} | {{flagZ ? 1 : 0}} | {{flagC ? 1 : 0}} | {{flagV ? 1 : 0}} |
Address Bus
Data Bus
RAM
{{(index - 1) + 'xx'}}
{{(index - 1) + 'xx'}}